1. Field of the Invention
The present invention generally relates to static random-access memory (SRAM), and, more specifically, to a technique for optimizing SRAM passive power consumption.
2. Description of the Related Art
A conventional SRAM module includes one or more bit cell rows that each includes a collection of bit cells. Each bit cell within a given bit cell row is configured to store an individual bit of data, i.e. a logical “0” or “1.” A wordline coupled to the bit cell row provides write and read access to all of the bit cells within that row.
When performing a memory access operation, the bit lines of all the columns in the bit cell row are pre-changed before the memory access operation can take place. The SRAM may then perform the memory access operation by asserting a column select signal with the targeted bit cells. The memory access operation could be, e.g., a write operation that involves writing a word of data to the targeted bit cells, or a read operation that involves reading a word of data from the targeted bit cells. During a read operation, all the bit cells are activated and thus the bit line of all columns are discharged. During a write operation, the bit lines of targeted bit cells are written with a desired value and all other bit lines undergo a passive read, and these non-targeted cells dissipate excess power.
A given bit cell row may include numerous bit cells capable of storing multiple different words of data. However, when a memory access operation requires access to just one of those words of data, the SRAM module must enable the wordline for the entire row, thereby pre-charging all of the bit cells within that row. This approach is problematic because enabling bit cells that are not required for the memory access operation wastes power.
Accordingly, what is needed in the art is a more effective technique for performing memory access operations with an SRAM module.